Modern data processing equipment utilize video display devices which provide a wide range of picture element (pixel) resolutions. For example, a computer graphics adapter (CGA) video interface card for an IBM-compatible personal computer provides a video image having 64,000 (320.times.200) pixel or dot positions in each displayed image, while a high-resolution 1 k variable graphics adapter (VGA) video interface card provides 786,432 (1024.times.768) pixel positions. Each of these video images is displayed in about the same amount of time, consequently, the frequency of the clock signal used to display the 1 k VGA image is approximately twelve times that of the signal used to display the CGA image. In addition, there are other computer graphic interfaces which provide even greater resolution and thus, employ even higher-frequency dot clock signals.
In some computer graphics applications, it may be desirable to provide several levels of resolution. For example, a relatively low resolution display format may be preferred for preparing text or for determining image layout, since the smaller number of pixels in the image may translate to less elapsed time to generate or change the image. However, a relatively high-resolution display format may be preferred for applications such as desktop publishing in which high-quality text may be combined with high-resolution graphic images.
A high performance VGA interface card, such as the VGA Wonder.sup.tm available from ATI Technologies Inc., is compatible with several video graphic display formats including CGA, EGA (640.times.350), VGA (640.times.480), Super VGA (800.times.600) and 1 k VGA. In addition, the interface card supports text display formats having fewer pixels per screen image than even CGA. A flexible video interface of this type may use several different pixel clock signals having frequencies that range from approximately 100 MHz for the 1 k VGA format to approximately 20 MHz for the CGA and text display formats.
In addition to the high speed pixel clock signals supported by the video graphic interface cards, there is also a requirement for other high speed clock signals to perform functions such as parallel loading the video shift register and memory refresh on the video RAMs or DRAMs. Thus it would be advantageous for a clock signal generator to be capable of producing two separate, programmable frequency clock signals. It would be a further advantage if the two clock signals could be generated on a single integrated circuit (IC) using a single reference crystal oscillator or other reference source.
Many of the currently available video display interface cards employ several clock oscillators to produce these different clock signal frequencies. This duplication of circuitry increases the complexity and cost of the video display card over that of a multi-frequency card which employs a single oscillator having a single resonant crystal.
One integrated circuit which generates clock signals uses a single reference to produce two independent clock signals is the WD90C60, available from Western Digital Imaging. From a 14 MHz source, a video clock signal (VCLK) and memory clock signal (MCLK) are produced. The VCLK signal may have a frequency of either 25 MHz or 28 MHz. This frequency is dynamically alterable under firmware control. The MCLK signal is jumper selectable between 36 MHz (for 120 ns DRAMs) and 42 MHz (for 100 ns DRAMs). In addition to these two internally generated clock signals, up to three external clock signals may be multiplexed with the internally generated video clock signal, and may be selected as the video clock signal by setting a mode control register. Also in the same product family is the WD90C61, which provides one of eight clock signal frequencies for the VCLK output signal, and one of four clock signal frequencies for the MCLK output signal.
Another dual clock signal generator IC currently available is Avasem Corporation's AV9114 Dual Video Frequency Generator. This integrated circuit provides a first internally generated clock signal, which may range in frequency from 14 MHz to 40 MHz, at its CLK0 output terminal, and a second clock signal, CLK1, which may range in frequency from 16 MHz to 50 MHz. As with the WD90C60, the capability exists for one of three external clock signals to be selected as the output signal CLK0 in place of the internally generated signal. However, neither of these two integrated circuits is capable of generating the high frequencies demanded by the high resolution video graphics interfaces such as the 1 k VGA standard discussed above.
A problem is known to exist when phase-locked loops (PLLs) are used to generate two independent clock signal frequencies on the same integrated circuit. When the signals generated by the video controller chip happen to be close to one another in frequency or phase, users have observed a severe degradation in both clock signals due to cross-signal interference. This interference occurs because the voltage controlled oscillator (VCO) within each PLL tries to lock to the frequency produced by the other oscillator. This causes the VCOs to drift, rendering the generated clock signals unusable for their intended application. To avoid this problem, users of currently available circuits which generate two clock signals must ensure that two conflicting frequencies are never selected for the signals. This limits the flexibility of the systems designed with these circuits.